1. Field of the Invention
The present invention relates to a memory controlling device, and particularly to a memory controlling device controlling access to a memory having a plurality of banks and a processing method thereof.
2. Description of the Related Art
Heretofore, a synchronous DRAM (SDRAM: Synchronous Dynamic Random Access Memory), which is advantageous in terms of price, bus band, and capacity, is widely used as a memory system. This SDRAM is a DRAM operating in synchronism with a clock signal, and is formed by a plurality of banks in many cases.
When different rows in an identical bank are consecutively accessed in the SDRAM of such a configuration, efficiency of data transfer in the SDRAM is decreased significantly. On the other hand, a large number of methods for suppressing the decrease in the efficiency of data transfer have been devised. For example, a method has been proposed which makes two buffers retain respective access requests to access a memory and which outputs an access request selected from the retained access requests and indicating a bank address different from a bank address accessed at a previous time (see Japanese Patent Laid-Open No. 2003-186740 (FIG. 1), for example).